Conventional flip-flops, for example, conventional complementary metal-oxide semiconductor (CMOS) flip-flops), are generally volatile. With the advent of deep sub-micron CMOS technology, leakage power increases significantly while squeezing more performance on smaller area and supply voltages. In particular, conventional CMOS registers suffer significant power loss from off-state (static) leakage. For example, during idle mode, data has to be transferred to shadow latch and power supply has to be maintained to hold the data, which consumes leakage power. In other words, shadow latch needs to be power-on during idle mode and is susceptible to leakage current and consumes leakage power. Data may also be transferred to a flash memory, which typically has limited speed performance and requires high control voltage. The flash memory also faces challenges in scaling below 20 nm. Further, the saving and reloading of data to/from the flash memory increases the wake-up time from idle mode to normal operation. Extra or additional circuits may be needed for the control of “save” and “reload” operations.
Non-volatile registers or flip-flops (nvFFs) are envisaged to play an increasingly important role as they may be powered-off in sleep mode (or idle mode) with zero leakage. Various non-volatile flip-flops have been proposed, which have zero power consumption in idle mode. Conventional non-volatile flip-flops bear similar architectures to a static latch-based master-slave register. However, such non-volatile flip-flops, for example, resistive non-volatile flip-flops, are generally slow because of static differential latch architecture that has high parasitic capacitance (e.g., at the internal nodes of the flip-flops) and therefore not suitable for ultra-high speed and low-power arithmetic logic unit (ALU) registers, register files and cache applications.
A spin-transfer torque magnetic random-access memory (STTMRAM) is a promising candidate for nvFF due to its high write speed and endurance cycle, low write power and zero standby power. In other words, for the STTMRAM with high endurance and low write energy, “save” and “reload” operations may not be required. nvFFs with STT-MRAM have been mainly proposed to address the leakage current issue. Typically, these nvFFs resemble a sense-amplifier based master-slave register, and have cross-coupled inverters as the output stage. This type of registers poses delay issue, due to the inherent latch time of the cross-coupled inverters and the high parasitic capacitance at the internal nodes.
FIG. 1 shows a simplified representative diagram 100 illustrating typical access times of memory in computer systems. Various stages may involve different access times. For example, a storage 102 may have an access time of about 1 ms, a memory 104 may have an access time of about 10-30 ns, a cache (level 2 (L2), or level 3 (L3)) 106 may have an access time of about 3-10 ns, and a logic/flip-flop/register file cache (level 1 (L1)) 108 may have an access time of less than 1 ns. A resistive random-access memory (RRAM) 110 may be employed for the storage 102, the memory 104, and the cache (L2, L3) 106, and a STT-MRAM 112 may be employed for the memory 104, the cache (L2, L3) 106, and the logic/flip-flop/register file cache (L1) 108. Conventional non-volatile flip-flops are generally too slow for high performance logic applications, register files and L1-L3 cache in a high speed microprocessor.
To achieve high performance, especially in portable applications, non-volatile flip-flops need to be both fast and energy-efficient.